first working CPU implementation with 3 op codes

src/bus.rs

@@ -10,15 +10,21 @@ pub struct NesBus {
     cart: Cartridge,
 }
 
+impl NesBus {
+    pub fn new(cart: Cartridge) -> Self {
+        Self { ram: [0; 0x800], cart }
+    }
+}
+
 impl Bus for NesBus {
     fn read(&mut self, address: u16) -> u8 {
         match address {
             0x0000..=0x1FFF => self.ram[(address & 0x07FF) as usize], // Zero-Page my beloved
             0x2000..=0x3FFF => 0, //PPU registers stub, temporal
             0x4000..=0x401F => 0, //APU controller stub, temporal
-            0x4020..=0x5FFF => 0, //Expansion ROM stub
+            0x4020..=0x5FFF => 0, //Expansion ROM stub. temporal
             0x6000..=0x7FFF => 0, //SRAM stub, no reading saves for you :3
-            0x8000..=0xFFFF => self.cart.read_prg(address),
+            0x8000..=0xFFFF => self.cart.read_prg(address), // this is te space PRG Rom gets "loaded" to in real hardware
         }
     }