implemented bus to then start with the CPU

src/bus.rs

@@ -0,0 +1,31 @@
+use crate::cartridge::Cartridge;
+
+pub trait Bus {
+    fn read(&mut self, address: u16) -> u8;
+    fn write(&mut self, address: u16, value: u8);
+}
+
+pub struct NesBus {
+    ram: [u8; 0x800], // 2KB fixed array, mirrors to fill $0000 to $1FFF
+    cart: Cartridge,
+}
+
+impl Bus for NesBus {
+    fn read(&mut self, address: u16) -> u8 {
+        match address {
+            0x0000..=0x1FFF => self.ram[(address & 0x07FF) as usize], // Zero-Page my beloved
+            0x2000..=0x3FFF => 0, //PPU registers stub, temporal
+            0x4000..=0x401F => 0, //APU controller stub, temporal
+            0x4020..=0x5FFF => 0, //Expansion ROM stub
+            0x6000..=0x7FFF => 0, //SRAM stub, no reading saves for you :3
+            0x8000..=0xFFFF => self.cart.read_prg(address),
+        }
+    }
+
+    fn write(&mut self, address: u16, value: u8) {
+        match address {
+            0x0000..=0x1FFF => self.ram[(address & 0x07FF) as usize] = value,
+            _ => {} // Everything else dropped for now
+        }
+    }
+}

src/main.rs

@@ -1,4 +1,5 @@
 mod cartridge;
+mod bus;
 
 fn main() {
     println!("Hello, world!");