implemented branching operations

STATE.md

@@ -21,7 +21,9 @@
   - step dispatch shell + trace in nestest format
   - set_test_start for the nestest harness
 - nestest harness working (main.rs): loads nestest.nes, runs from $C000 with CYC:7, dumps trace to ours.log
-- First 5 trace lines match the nestest reference log exactly (PC, regs, P, SP, CYC), then it panics on the next unimplemented opcode (JSR 0x20), which names the next target
+- Batch 1 done (subroutines + stack): JSR, RTS, PHA, PLA, PHP, PLP, RTI, BRK, plus NOP and SEC as quick wins. Verified SP:FD->FB across JSR (push high-then-low works)
+- Trace now matches the nestest reference log through line 8 (C72E SEC, CYC:29). Next panic is on BCS 0xB0 at line 9 (Batch 2)
+- trace bytes are length-aware via opcode_len (fixed-width byte field, columns align for awk diff)
 
 ## Next
 
@@ -29,8 +31,8 @@ Finish the official CPU. Nestest analysis findings: the full 8991-line log tests
 
 CPU implementation batches (by family, ordered by nestest log frequency):
 
-- Batch 1 - Subroutines + stack: JSR 0x20 (push ret-1 high then low), RTS 0x60 (pop low then high), PHA 0x48, PLA 0x68, PHP 0x08, PLP 0x28 (B-flag on push rule), RTI 0x40, BRK 0x00
-- Batch 2 - Branches (all 8): BEQ F0, BNE D0, BCC 90, BCS B0, BPL 10, BMI 30, BVC 50, BVS 70. One shared method per flag. +1 cycle if taken, +1 more if target crosses page
+- Batch 1 - DONE (see Done section)
+- Batch 2 - Branches (all 8): BEQ F0, BNE D0, BCC 90, BCS B0, BPL 10, BMI 30, BVC 50, BVS 70. One shared method per flag. +1 cycle if taken, +1 more if target crosses page. Next up
 - Batch 3 - Loads: LDA 8 modes, LDX 5 modes, LDY 5 modes (share load + set_zp_flags)
 - Batch 4 - Stores: STA 7 modes, STX 3, STY 3 (share store core, no flag changes)
 - Batch 5 - Compares: CMP 8 modes, CPX 3, CPY 3 (set C/Z/N, no store)