implemented SBC, ADC and BIT family of instruction, .logs match now 73 instructions on nestest
This commit is contained in:
@@ -27,6 +27,7 @@
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- Trace now matches the nestest reference log through line 38 (C782 BIT, CYC:98), field-for-field (PC/A/X/Y/P/SP/CYC verified by label-comparison script). Next panic is on 0x24 (BIT zp) at line 38, top of Batch 6
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- Batch 3 done (loads): LDA (8 modes), LDX (5 modes), LDY (5 modes) via three shared cores (lda/ldx/ldy) + thin wrappers. Caught two real bugs in review: all 4 LDY wrappers called self.ldx (would write to X instead of Y), and 6 of 8 LDX/LDY wrappers had wrong base cycles (3 instead of 4). Both fixed
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- Batch 4 done (stores): STA (7 modes), STX (3 modes), STY (3 modes) via three shared cores (sta/stx/sty) + thin wrappers. No flag changes. Refactored stx_zp to use the shared stx core for consistency. Fixed a comment typo (sta_abx was labeled 0x95 instead of 0x9D)
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- Batch 5 done (compares): CMP (8 modes), CPX (3 modes), CPY (3 modes) via three shared cores (cmp/cpx/cpy) + wrappers + immediate variants. Sets C (reg >= mem), Z, N; no store. Uses wrapping_sub for the borrow math. 70 of 151 official opcodes done. No diff progress expected until the log reaches these opcodes
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- trace bytes are length-aware via opcode_len (fixed-width byte field, columns align for awk diff)
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## Next
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@@ -39,8 +40,8 @@ CPU implementation batches (by family, ordered by nestest log frequency):
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- Batch 2 - DONE (branches, see Done section)
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- Batch 3 - DONE (loads, see Done section)
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- Batch 4 - DONE (stores, see Done section)
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- Batch 5 - Compares: CMP 8 modes, CPX 3, CPY 3 (set C/Z/N, no store). Next up. Note: keeping family order on purpose, no diff progress until the log reaches these opcodes
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- Batch 6 - Arithmetic: ADC 8 modes, SBC 8 modes (N/V/C/Z, decimal flag inert), BIT 2 modes
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- Batch 5 - DONE (compares, see Done section)
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- Batch 6 - Arithmetic: ADC 8 modes, SBC 8 modes (N/V/C/Z, decimal flag inert), BIT 2 modes. Next up
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- Batch 7 - Logic: AND, ORA, EOR (8 modes each)
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- Batch 8 - Inc/Dec: INC/DEC 4 modes each (RMW), INX, INY, DEX, DEY
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- Batch 9 - Shifts: ASL, LSR, ROL, ROR (accumulator + 4 memory modes each, RMW)
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@@ -35,4 +35,39 @@ C776 4C 7D C7 A:00 X:00 Y:00 P:26 SP:FB CYC:88
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C77D EA A:00 X:00 Y:00 P:26 SP:FB CYC:91
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C77E A9 FF A:00 X:00 Y:00 P:26 SP:FB CYC:93
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C780 85 01 A:FF X:00 Y:00 P:A4 SP:FB CYC:95
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C782 24 A:FF X:00 Y:00 P:A4 SP:FB CYC:98
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C782 24 01 A:FF X:00 Y:00 P:A4 SP:FB CYC:98
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C784 70 04 A:FF X:00 Y:00 P:E4 SP:FB CYC:101
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C78A EA A:FF X:00 Y:00 P:E4 SP:FB CYC:104
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C78B 24 01 A:FF X:00 Y:00 P:E4 SP:FB CYC:106
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C78D 50 03 A:FF X:00 Y:00 P:E4 SP:FB CYC:109
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C78F 4C 96 C7 A:FF X:00 Y:00 P:E4 SP:FB CYC:111
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C796 EA A:FF X:00 Y:00 P:E4 SP:FB CYC:114
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C797 A9 00 A:FF X:00 Y:00 P:E4 SP:FB CYC:116
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C799 85 01 A:00 X:00 Y:00 P:66 SP:FB CYC:118
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C79B 24 01 A:00 X:00 Y:00 P:66 SP:FB CYC:121
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C79D 50 04 A:00 X:00 Y:00 P:26 SP:FB CYC:124
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C7A3 EA A:00 X:00 Y:00 P:26 SP:FB CYC:127
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C7A4 24 01 A:00 X:00 Y:00 P:26 SP:FB CYC:129
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C7A6 70 03 A:00 X:00 Y:00 P:26 SP:FB CYC:132
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C7A8 4C AF C7 A:00 X:00 Y:00 P:26 SP:FB CYC:134
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C7AF EA A:00 X:00 Y:00 P:26 SP:FB CYC:137
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C7B0 A9 00 A:00 X:00 Y:00 P:26 SP:FB CYC:139
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C7B2 10 04 A:00 X:00 Y:00 P:26 SP:FB CYC:141
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C7B8 EA A:00 X:00 Y:00 P:26 SP:FB CYC:144
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C7B9 A9 80 A:00 X:00 Y:00 P:26 SP:FB CYC:146
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C7BB 10 03 A:80 X:00 Y:00 P:A4 SP:FB CYC:148
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C7BD 4C D9 C7 A:80 X:00 Y:00 P:A4 SP:FB CYC:150
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C7D9 EA A:80 X:00 Y:00 P:A4 SP:FB CYC:153
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C7DA 60 A:80 X:00 Y:00 P:A4 SP:FB CYC:155
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C600 20 DB C7 A:80 X:00 Y:00 P:A4 SP:FD CYC:161
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C7DB EA A:80 X:00 Y:00 P:A4 SP:FB CYC:167
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C7DC A9 FF A:80 X:00 Y:00 P:A4 SP:FB CYC:169
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C7DE 85 01 A:FF X:00 Y:00 P:A4 SP:FB CYC:171
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C7E0 24 01 A:FF X:00 Y:00 P:A4 SP:FB CYC:174
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C7E2 A9 00 A:FF X:00 Y:00 P:E4 SP:FB CYC:177
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C7E4 38 A:00 X:00 Y:00 P:66 SP:FB CYC:179
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C7E5 78 A:00 X:00 Y:00 P:67 SP:FB CYC:181
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C7E6 F8 A:00 X:00 Y:00 P:67 SP:FB CYC:183
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C7E7 08 A:00 X:00 Y:00 P:6F SP:FB CYC:185
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C7E8 68 A:00 X:00 Y:00 P:6F SP:FA CYC:188
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C7E9 29 A:7F X:00 Y:00 P:6D SP:FB CYC:192
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+171
-1
@@ -166,6 +166,24 @@ impl Cpu {
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0xC0 => self.cpy_imm(bus),
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0xC4 => self.cpy_zp(bus),
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0xCC => self.cpy_abs(bus),
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0x69 => self.adc_imm(bus),
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0x65 => self.adc_zp(bus),
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0x75 => self.adc_zpx(bus),
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0x6D => self.adc_abs(bus),
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0x7D => self.adc_abx(bus),
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0x79 => self.adc_aby(bus),
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0x61 => self.adc_izx(bus),
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0x71 => self.adc_izy(bus),
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0xE9 => self.sbc_imm(bus),
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0xE5 => self.sbc_zp(bus),
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0xF5 => self.sbc_zpx(bus),
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0xED => self.sbc_abs(bus),
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0xFD => self.sbc_abx(bus),
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0xF9 => self.sbc_aby(bus),
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0xE1 => self.sbc_izx(bus),
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0xF1 => self.sbc_izy(bus),
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0x24 => self.bit_zp(bus),
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0x2C => self.bit_abs(bus),
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_ => panic!("illegal/unkown opcode {opcode:#04X} at {:#06X}", self.pc.wrapping_sub(1)),
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};
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self.cycles += cycles as u64;
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@@ -324,6 +342,46 @@ impl Cpu {
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base + extra
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}
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// shared add/sbc cores (based on adding the complement)
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fn add_with_carry(&mut self, value: u8) {
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let carry = if self.flag(FLAG_CARRY) { 1u16 } else { 0 };
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let sum = self.a as u16 + value as u16 + carry;
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let result = sum as u8;
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if sum > 0xFF { self.set_flag(FLAG_CARRY); } else { self.clear_flag(FLAG_CARRY); }
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if (self.a ^ result) & (value ^ result) & 0x80 != 0 {
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self.set_flag(FLAG_OVERFLOW);
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} else {
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self.clear_flag(FLAG_OVERFLOW);
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}
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self.set_zp_flags(result);
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self.a = result;
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}
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fn adc(&mut self, bus: &mut impl Bus, (address, extra): (u16, u8), base: u8) -> u8 {
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let value = self.read(bus, address);
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self.add_with_carry(value); // add as-is
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base + extra
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}
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fn sbc(&mut self, bus: &mut impl Bus, (address, extra): (u16, u8), base: u8) -> u8 {
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let value = self.read(bus, address);
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self.add_with_carry(!value); // add the complement => subtract
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base + extra
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}
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// BIT core
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fn bit(&mut self, bus: &mut impl Bus, (address, extra): (u16, u8), base: u8) -> u8 {
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let value = self.read(bus, address);
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self.clear_flag(FLAG_ZERO);
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if self.a & value == 0 { self.set_flag(FLAG_ZERO); }
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self.clear_flag(FLAG_NEGATIVE);
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if value & 0x80 != 0 { self.set_flag(FLAG_NEGATIVE); }
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self.clear_flag(FLAG_OVERFLOW);
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if value & 0x40 != 0 { self.set_flag(FLAG_OVERFLOW); }
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base + extra
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}
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// NES 6502 opcode -> functions
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fn jmp_abs(&mut self, bus: &mut impl Bus) -> u8 { // 0x4C, 3 bytes, 3 cycles
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@@ -663,7 +721,101 @@ impl Cpu {
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2
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}
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// ADC variants
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fn adc_zp(&mut self, bus: &mut impl Bus) -> u8 { // 0x65, 2 bytes, 3 cycles
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let (address, extra) = self.address_zp(bus);
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self.adc(bus, (address, extra), 3)
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}
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fn adc_zpx(&mut self, bus: &mut impl Bus) -> u8 { // 0x75, 2 bytes, 4 cycles
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let (address, extra) = self.address_zpx(bus);
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self.adc(bus, (address, extra), 4)
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}
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fn adc_abs(&mut self, bus: &mut impl Bus) -> u8 { // 0x6D, 3 bytes, 4 cycles
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let (address, extra) = self.address_abs(bus);
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self.adc(bus, (address, extra), 4)
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}
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fn adc_abx(&mut self, bus: &mut impl Bus) -> u8 { // 0x7D, 3 bytes, 4 cycles
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let (address, extra) = self.address_abx(bus);
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self.adc(bus, (address, extra), 4)
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}
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fn adc_aby(&mut self, bus: &mut impl Bus) -> u8 { // 0x79, 3 bytes, 4 cycles
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let (address, extra) = self.address_aby(bus);
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self.adc(bus, (address, extra), 4)
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}
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fn adc_izx(&mut self, bus: &mut impl Bus) -> u8 { // 0x61, 2 bytes, 6 cycles
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let (address, extra) = self.address_izx(bus);
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self.adc(bus, (address, extra), 6)
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}
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fn adc_izy(&mut self, bus: &mut impl Bus) -> u8 { // 0x71, 2 bytes, 5 cycles
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let (address, extra) = self.address_izy(bus);
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self.adc(bus, (address, extra), 5)
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}
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// SBC variants
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fn sbc_zp(&mut self, bus: &mut impl Bus) -> u8 { // 0xE5, 2 bytes, 3 cycles
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let (address, extra) = self.address_zp(bus);
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self.sbc(bus, (address, extra), 3)
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}
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fn sbc_zpx(&mut self, bus: &mut impl Bus) -> u8 { // 0xF5, 2 bytes, 4 cycles
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let (address, extra) = self.address_zpx(bus);
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self.sbc(bus, (address, extra), 4)
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}
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fn sbc_abs(&mut self, bus: &mut impl Bus) -> u8 { // 0xED, 3 bytes, 4 cycles
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let (address, extra) = self.address_abs(bus);
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self.sbc(bus, (address, extra), 4)
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}
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fn sbc_abx(&mut self, bus: &mut impl Bus) -> u8 { // 0xFD, 3 bytes, 4 cycles
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let (address, extra) = self.address_abx(bus);
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self.sbc(bus, (address, extra), 4)
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}
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fn sbc_aby(&mut self, bus: &mut impl Bus) -> u8 { // 0xF9, 3 bytes, 4 cycles
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let (address, extra) = self.address_aby(bus);
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self.sbc(bus, (address, extra), 4)
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}
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fn sbc_izx(&mut self, bus: &mut impl Bus) -> u8 { // 0xE1, 2 bytes, 6 cycles
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let (address, extra) = self.address_izx(bus);
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self.sbc(bus, (address, extra), 6)
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}
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fn sbc_izy(&mut self, bus: &mut impl Bus) -> u8 { // 0xF1, 2 bytes, 5 cycles
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let (address, extra) = self.address_izy(bus);
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self.sbc(bus, (address, extra), 5)
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}
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// BIT variants
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fn bit_zp(&mut self, bus: &mut impl Bus) -> u8 { // 0x24, 2 bytes, 3 cycles
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let (address, extra) = self.address_zp(bus);
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self.bit(bus, (address, extra), 3)
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}
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fn bit_abs(&mut self, bus: &mut impl Bus) -> u8 { // 0x2C, 3 bytes, 4 cycles
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let (address, extra) = self.address_abs(bus);
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self.bit(bus, (address, extra), 4)
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}
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// ADC/SBC immediate variants
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fn adc_imm(&mut self, bus: &mut impl Bus) -> u8 { // 0x69, 2 bytes, 2 cycles
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let value = self.fetch(bus);
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self.add_with_carry(value);
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2
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}
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fn sbc_imm(&mut self, bus: &mut impl Bus) -> u8 { // 0xE9, 2 bytes, 2 cycles
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let value = self.fetch(bus);
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self.add_with_carry(!value);
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2
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}
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// all branching alternatives here all 1 bytes
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fn bcs_rel(&mut self, bus: &mut impl Bus) -> u8 { self.branch(bus, self.flag(FLAG_CARRY)) } // 0xB0
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@@ -748,6 +900,24 @@ impl Cpu {
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0xC0 => 2, // CPY imm
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0xC4 => 2, // CPY zp
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0xCC => 3, // CPY abs
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0x69 => 2, // ADC imm
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0x65 => 2, // ADC zp
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0x75 => 2, // ADC zpx
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0x6D => 3, // ADC abs
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0x7D => 3, // ADC abx
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0x79 => 3, // ADC aby
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0x61 => 2, // ADC izx
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0x71 => 2, // ADC izy
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0xE9 => 2, // SBC imm
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0xE5 => 2, // SBC zp
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0xF5 => 2, // SBC zpx
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0xED => 3, // SBC abs
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0xFD => 3, // SBC abx
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0xF9 => 3, // SBC aby
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0xE1 => 2, // SBC izx
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0xF1 => 2, // SBC izy
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0x24 => 2, // BIT zp
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0x2C => 3, // BIT abs
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_ => 1, // fallback, would show the invalid/unknown opcode only not its parameters
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}
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}
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