changed format of match tables to use 4 matches per line to have a more compact layout
This commit is contained in:
+67
-181
@@ -96,100 +96,81 @@ impl Cpu {
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pub fn step(&mut self, bus: &mut impl Bus) -> u8 {
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let opcode: u8 = self.fetch(bus);
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let cycles = match opcode {
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0x4C => self.jmp_abs(bus),
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0xA2 => self.ldx_imm(bus),
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0x86 => self.stx_zp(bus),
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0x20 => self.jsr_abs(bus),
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0x60 => self.rts_imp(bus),
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0x48 => self.pha_imp(bus),
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0x68 => self.pla_imp(bus),
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0x08 => self.php_imp(bus),
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// Jumps & subroutines
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0x4C => self.jmp_abs(bus), 0x20 => self.jsr_abs(bus), 0x60 => self.rts_imp(bus),
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0x40 => self.rti_imp(bus), 0x00 => self.brk_imp(bus),
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// Stack
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0x48 => self.pha_imp(bus), 0x68 => self.pla_imp(bus), 0x08 => self.php_imp(bus),
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0x28 => self.plp_imp(bus),
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0x40 => self.rti_imp(bus),
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0x00 => self.brk_imp(bus),
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0xEA => self.nop_imp(bus),
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0x38 => self.sec_imp(bus),
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0x90 => self.bcc_rel(bus),
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0xB0 => self.bcs_rel(bus),
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0xF0 => self.beq_rel(bus),
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0xD0 => self.bne_rel(bus),
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0x10 => self.bpl_rel(bus),
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0x30 => self.bmi_rel(bus),
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0x50 => self.bvc_rel(bus),
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0x70 => self.bvs_rel(bus),
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0x18 => self.clc_imp(bus),
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0x58 => self.cli_imp(bus),
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0xB8 => self.clv_imp(bus),
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0xD8 => self.cld_imp(bus),
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0x78 => self.sei_imp(bus),
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0xF8 => self.sed_imp(bus),
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0xA9 => self.lda_imm(bus),
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0xA5 => self.lda_zp(bus),
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0xB5 => self.lda_zpx(bus),
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0xAD => self.lda_abs(bus),
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0xBD => self.lda_abx(bus),
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0xB9 => self.lda_aby(bus),
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0xA1 => self.lda_izx(bus),
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0xB1 => self.lda_izy(bus),
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0xA6 => self.ldx_zp(bus),
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0xB6 => self.ldx_zpy(bus),
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0xAE => self.ldx_abs(bus),
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0xBE => self.ldx_aby(bus),
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0xA0 => self.ldy_imm(bus),
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0xA4 => self.ldy_zp(bus),
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0xB4 => self.ldy_zpx(bus),
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0xAC => self.ldy_abs(bus),
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0xBC => self.ldy_abx(bus),
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0x85 => self.sta_zp(bus),
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0x95 => self.sta_zpx(bus),
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0x8D => self.sta_abs(bus),
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0x9D => self.sta_abx(bus),
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0x99 => self.sta_aby(bus),
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0x81 => self.sta_izx(bus),
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0x91 => self.sta_izy(bus),
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0x96 => self.stx_zpy(bus),
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0x8E => self.stx_abs(bus),
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0x84 => self.sty_zp(bus),
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0x94 => self.sty_zpx(bus),
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// Flags & misc
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0x38 => self.sec_imp(bus), 0x18 => self.clc_imp(bus), 0x58 => self.cli_imp(bus),
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0x78 => self.sei_imp(bus), 0xD8 => self.cld_imp(bus), 0xF8 => self.sed_imp(bus),
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0xB8 => self.clv_imp(bus), 0xEA => self.nop_imp(bus),
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// Branches
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0x90 => self.bcc_rel(bus), 0xB0 => self.bcs_rel(bus), 0xF0 => self.beq_rel(bus),
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0xD0 => self.bne_rel(bus), 0x10 => self.bpl_rel(bus), 0x30 => self.bmi_rel(bus),
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0x50 => self.bvc_rel(bus), 0x70 => self.bvs_rel(bus),
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// Loads
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0xA9 => self.lda_imm(bus), 0xA5 => self.lda_zp(bus), 0xB5 => self.lda_zpx(bus),
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0xAD => self.lda_abs(bus), 0xBD => self.lda_abx(bus), 0xB9 => self.lda_aby(bus),
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0xA1 => self.lda_izx(bus), 0xB1 => self.lda_izy(bus), 0xA2 => self.ldx_imm(bus),
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0xA6 => self.ldx_zp(bus), 0xB6 => self.ldx_zpy(bus), 0xAE => self.ldx_abs(bus),
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0xBE => self.ldx_aby(bus), 0xA0 => self.ldy_imm(bus), 0xA4 => self.ldy_zp(bus),
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0xB4 => self.ldy_zpx(bus), 0xAC => self.ldy_abs(bus), 0xBC => self.ldy_abx(bus),
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// Stores
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0x85 => self.sta_zp(bus), 0x95 => self.sta_zpx(bus), 0x8D => self.sta_abs(bus),
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0x9D => self.sta_abx(bus), 0x99 => self.sta_aby(bus), 0x81 => self.sta_izx(bus),
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0x91 => self.sta_izy(bus), 0x86 => self.stx_zp(bus), 0x96 => self.stx_zpy(bus),
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0x8E => self.stx_abs(bus), 0x84 => self.sty_zp(bus), 0x94 => self.sty_zpx(bus),
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0x8C => self.sty_abs(bus),
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0xC9 => self.cmp_imm(bus),
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0xC5 => self.cmp_zp(bus),
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0xD5 => self.cmp_zpx(bus),
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0xCD => self.cmp_abs(bus),
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0xDD => self.cmp_abx(bus),
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0xD9 => self.cmp_aby(bus),
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0xC1 => self.cmp_izx(bus),
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0xD1 => self.cmp_izy(bus),
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0xE0 => self.cpx_imm(bus),
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0xE4 => self.cpx_zp(bus),
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0xEC => self.cpx_abs(bus),
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0xC0 => self.cpy_imm(bus),
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0xC4 => self.cpy_zp(bus),
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0xCC => self.cpy_abs(bus),
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0x69 => self.adc_imm(bus),
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0x65 => self.adc_zp(bus),
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0x75 => self.adc_zpx(bus),
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0x6D => self.adc_abs(bus),
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0x7D => self.adc_abx(bus),
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0x79 => self.adc_aby(bus),
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0x61 => self.adc_izx(bus),
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0x71 => self.adc_izy(bus),
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0xE9 => self.sbc_imm(bus),
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0xE5 => self.sbc_zp(bus),
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0xF5 => self.sbc_zpx(bus),
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0xED => self.sbc_abs(bus),
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0xFD => self.sbc_abx(bus),
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0xF9 => self.sbc_aby(bus),
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0xE1 => self.sbc_izx(bus),
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0xF1 => self.sbc_izy(bus),
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0x24 => self.bit_zp(bus),
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0x2C => self.bit_abs(bus),
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// Compares
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0xC9 => self.cmp_imm(bus), 0xC5 => self.cmp_zp(bus), 0xD5 => self.cmp_zpx(bus),
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0xCD => self.cmp_abs(bus), 0xDD => self.cmp_abx(bus), 0xD9 => self.cmp_aby(bus),
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0xC1 => self.cmp_izx(bus), 0xD1 => self.cmp_izy(bus), 0xE0 => self.cpx_imm(bus),
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0xE4 => self.cpx_zp(bus), 0xEC => self.cpx_abs(bus), 0xC0 => self.cpy_imm(bus),
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0xC4 => self.cpy_zp(bus), 0xCC => self.cpy_abs(bus),
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// Arithmetic
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0x69 => self.adc_imm(bus), 0x65 => self.adc_zp(bus), 0x75 => self.adc_zpx(bus),
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0x6D => self.adc_abs(bus), 0x7D => self.adc_abx(bus), 0x79 => self.adc_aby(bus),
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0x61 => self.adc_izx(bus), 0x71 => self.adc_izy(bus), 0xE9 => self.sbc_imm(bus),
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0xE5 => self.sbc_zp(bus), 0xF5 => self.sbc_zpx(bus), 0xED => self.sbc_abs(bus),
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0xFD => self.sbc_abx(bus), 0xF9 => self.sbc_aby(bus), 0xE1 => self.sbc_izx(bus),
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0xF1 => self.sbc_izy(bus), 0x24 => self.bit_zp(bus), 0x2C => self.bit_abs(bus),
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_ => panic!("illegal/unkown opcode {opcode:#04X} at {:#06X}", self.pc.wrapping_sub(1)),
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};
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self.cycles += cycles as u64;
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cycles
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}
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// NES 6502 opcode length table/matcher
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pub fn opcode_len(opcode: u8) -> u8 {
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match opcode {
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0x4C => 3, /* JMP abs */ 0xA2 => 2, /* LDX imm */ 0x86 => 2, /* STX zp */ 0x20 => 3, /* JSR abs */
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0x60 => 1, /* RTS imp */ 0x48 => 1, /* PHA imp */ 0x68 => 1, /* PLA imp */ 0x08 => 1, /* PHP imp */
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0x28 => 1, /* PLP imp */ 0x40 => 1, /* RTI imp */ 0x00 => 1, /* BRK imp */ 0xEA => 1, /* NOP */
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0x38 => 1, /* SEC imp */ 0x18 => 1, /* CLC imp */ 0x58 => 1, /* CLI imp */ 0x78 => 1, /* SEI imp */
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0xD8 => 1, /* CLD imp */ 0xF8 => 1, /* SED imp */ 0xB8 => 1, /* CLV imp */ 0x90 => 2, /* BCC rel */
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0xB0 => 2, /* BCS rel */ 0xF0 => 2, /* BEQ rel */ 0xD0 => 2, /* BNE rel */ 0x10 => 2, /* BPL rel */
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0x30 => 2, /* BMI rel */ 0x50 => 2, /* BVC rel */ 0x70 => 2, /* BVS rel */ 0xA9 => 2, /* LDA imm */
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0xA5 => 2, /* LDA zp */ 0xB5 => 2, /* LDA zpx */ 0xAD => 3, /* LDA abs */ 0xBD => 3, /* LDA abx */
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0xB9 => 3, /* LDA aby */ 0xA1 => 2, /* LDA izx */ 0xB1 => 2, /* LDA izy */ 0xA6 => 2, /* LDX zp */
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0xB6 => 2, /* LDX zpy */ 0xAE => 3, /* LDX abs */ 0xBE => 3, /* LDX aby */ 0xA0 => 2, /* LDY imm */
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0xA4 => 2, /* LDY zp */ 0xB4 => 2, /* LDY zpx */ 0xAC => 3, /* LDY abs */ 0xBC => 3, /* LDY abx */
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0x85 => 2, /* STA zp */ 0x95 => 2, /* STA zpx */ 0x8D => 3, /* STA abs */ 0x9D => 3, /* STA abx */
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0x99 => 3, /* STA aby */ 0x81 => 2, /* STA izx */ 0x91 => 2, /* STA izy */ 0x96 => 2, /* STX zpy */
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0x8E => 3, /* STX abs */ 0x84 => 2, /* STY zp */ 0x94 => 2, /* STY zpx */ 0x8C => 3, /* STY abs */
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0xC9 => 2, /* CMP imm */ 0xC5 => 2, /* CMP zp */ 0xD5 => 2, /* CMP zpx */ 0xCD => 3, /* CMP abs */
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0xDD => 3, /* CMP abx */ 0xD9 => 3, /* CMP aby */ 0xC1 => 2, /* CMP izx */ 0xD1 => 2, /* CMP izy */
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0xE0 => 2, /* CPX imm */ 0xE4 => 2, /* CPX zp */ 0xEC => 3, /* CPX abs */ 0xC0 => 2, /* CPY imm */
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0xC4 => 2, /* CPY zp */ 0xCC => 3, /* CPY abs */ 0x69 => 2, /* ADC imm */ 0x65 => 2, /* ADC zp */
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0x75 => 2, /* ADC zpx */ 0x6D => 3, /* ADC abs */ 0x7D => 3, /* ADC abx */ 0x79 => 3, /* ADC aby */
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0x61 => 2, /* ADC izx */ 0x71 => 2, /* ADC izy */ 0xE9 => 2, /* SBC imm */ 0xE5 => 2, /* SBC zp */
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0xF5 => 2, /* SBC zpx */ 0xED => 3, /* SBC abs */ 0xFD => 3, /* SBC abx */ 0xF9 => 3, /* SBC aby */
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0xE1 => 2, /* SBC izx */ 0xF1 => 2, /* SBC izy */ 0x24 => 2, /* BIT zp */ 0x2C => 3, /* BIT abs */
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_ => 1, // fallback, would show the invalid/unknown opcode only not its parameters
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}
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}
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// Trace for testing the cpu
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pub fn trace(&self, bus: &mut impl Bus) -> String {
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let opcode: u8 = bus.read(self.pc);
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@@ -827,100 +808,5 @@ impl Cpu {
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fn bvc_rel(&mut self, bus: &mut impl Bus) -> u8 { self.branch(bus, !self.flag(FLAG_OVERFLOW)) } // 0x50
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fn bvs_rel(&mut self, bus: &mut impl Bus) -> u8 { self.branch(bus, self.flag(FLAG_OVERFLOW)) } //0x70
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// NES 6502 opcode length table/matcher
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pub fn opcode_len(opcode: u8) -> u8 {
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match opcode {
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0x4C => 3, // JMP abs
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0xA2 => 2, // LDX imm
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0x86 => 2, // STX zp
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0x20 => 3, // JSR abs
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0x60 => 1, // RTS imp
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0x48 => 1, // PHA imp
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0x68 => 1, // PLA imp
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0x08 => 1, // PHP imp
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0x28 => 1, // PLP imp
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0x40 => 1, // RTI imp
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0x00 => 1, // BRK imp
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0xEA => 1, // NOP
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0x38 => 1, // SEC imp
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0x90 => 2, // BCC rel
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0xB0 => 2, // BCS rel
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0xF0 => 2, // BEQ rel
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0xD0 => 2, // BNE rel
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0x10 => 2, // BPL rel
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0x30 => 2, // BMI rel
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0x50 => 2, // BVC rel
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0x70 => 2, // BVS rel
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0x18 => 1, // CLC imp
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0x58 => 1, // CLI imp
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0xB8 => 1, // CLV imp
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0xD8 => 1, // CLD imp
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0x78 => 1, // SEI imp
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0xF8 => 1, // SED imp
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0xA9 => 2, // LDA imm
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0xA5 => 2, // LDA zp
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0xB5 => 2, // LDA zpx
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0xAD => 3, // LDA abs
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0xBD => 3, // LDA abx
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0xB9 => 3, // LDA aby
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0xA1 => 2, // LDA izx
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0xB1 => 2, // LDA izy
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0xA6 => 2, // LDX zp
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0xB6 => 2, // LDX zpy
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0xAE => 3, // LDX abs
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0xBE => 3, // LDX aby
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0xA0 => 2, // LDY imm
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0xA4 => 2, // LDY zp
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0xB4 => 2, // LDY zpx
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0xAC => 3, // LDY abs
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0xBC => 3, // LDY abx
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0x85 => 2, // STA zp
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0x95 => 2, // STA zpx
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0x8D => 3, // STA abs
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0x9D => 3, // STA abx
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0x99 => 3, // STA aby
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0x81 => 2, // STA izx
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0x91 => 2, // STA izy
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0x96 => 2, // STX zpy
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0x8E => 3, // STX abs
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0x84 => 2, // STY zp
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0x94 => 2, // STY zpx
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0x8C => 3, // STY abs
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0xC9 => 2, // CMP imm
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0xC5 => 2, // CMP zp
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0xD5 => 2, // CMP zpx
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0xCD => 3, // CMP abs
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0xDD => 3, // CMP abx
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0xD9 => 3, // CMP aby
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0xC1 => 2, // CMP izx
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0xD1 => 2, // CMP izy
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0xE0 => 2, // CPX imm
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0xE4 => 2, // CPX zp
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0xEC => 3, // CPX abs
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0xC0 => 2, // CPY imm
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0xC4 => 2, // CPY zp
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0xCC => 3, // CPY abs
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0x69 => 2, // ADC imm
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0x65 => 2, // ADC zp
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0x75 => 2, // ADC zpx
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0x6D => 3, // ADC abs
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0x7D => 3, // ADC abx
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0x79 => 3, // ADC aby
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0x61 => 2, // ADC izx
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0x71 => 2, // ADC izy
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0xE9 => 2, // SBC imm
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0xE5 => 2, // SBC zp
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0xF5 => 2, // SBC zpx
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0xED => 3, // SBC abs
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0xFD => 3, // SBC abx
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0xF9 => 3, // SBC aby
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0xE1 => 2, // SBC izx
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0xF1 => 2, // SBC izy
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0x24 => 2, // BIT zp
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0x2C => 3, // BIT abs
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_ => 1, // fallback, would show the invalid/unknown opcode only not its parameters
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}
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}
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}
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