implemented Clear and Set instructions for Flags

ours.log

@@ -9,3 +9,14 @@ C72E  38       A:00 X:00 Y:00 P:26 SP:FB CYC:29
 C72F  B0 04    A:00 X:00 Y:00 P:27 SP:FB CYC:31
 C735  EA       A:00 X:00 Y:00 P:27 SP:FB CYC:34
 C736  18       A:00 X:00 Y:00 P:27 SP:FB CYC:36
+C737  B0 03    A:00 X:00 Y:00 P:26 SP:FB CYC:38
+C739  4C 40 C7  A:00 X:00 Y:00 P:26 SP:FB CYC:40
+C740  EA       A:00 X:00 Y:00 P:26 SP:FB CYC:43
+C741  38       A:00 X:00 Y:00 P:26 SP:FB CYC:45
+C742  90 03    A:00 X:00 Y:00 P:27 SP:FB CYC:47
+C744  4C 4B C7  A:00 X:00 Y:00 P:27 SP:FB CYC:49
+C74B  EA       A:00 X:00 Y:00 P:27 SP:FB CYC:52
+C74C  18       A:00 X:00 Y:00 P:27 SP:FB CYC:54
+C74D  90 04    A:00 X:00 Y:00 P:26 SP:FB CYC:56
+C753  EA       A:00 X:00 Y:00 P:26 SP:FB CYC:59
+C754  A9       A:00 X:00 Y:00 P:26 SP:FB CYC:61

src/cpu.rs

@@ -117,6 +117,12 @@ impl Cpu {
             0x30 => self.bmi_rel(bus),
             0x50 => self.bvc_rel(bus),
             0x70 => self.bvs_rel(bus),
+            0x18 => self.clc_imp(bus),
+            0x58 => self.cli_imp(bus),
+            0xB8 => self.clv_imp(bus),
+            0xD8 => self.cld_imp(bus),
+            0x78 => self.sei_imp(bus),
+            0xF8 => self.sed_imp(bus),
             _ => panic!("illegal/unkown opcode {opcode:#04X} at {:#06X}", self.pc.wrapping_sub(1)),
         };
         self.cycles += cycles as u64;
@@ -297,9 +303,39 @@ impl Cpu {
         2
     }
 
-    // all branching alternatives here all 2 bytes
-    fn bcs_rel(&mut self, bus: &mut impl Bus) -> u8 { self.branch(bus, self.flag(FLAG_CARRY)) } // 0x90
-    fn bcc_rel(&mut self, bus: &mut impl Bus) -> u8 { self.branch(bus, !self.flag(FLAG_CARRY)) } // 0xB0
+    fn clc_imp(&mut self, _bus: &mut impl Bus) -> u8 { // 0x18, 1 byte, 2 cycles
+        self.clear_flag(FLAG_CARRY);
+        2
+    }
+
+    fn cli_imp(&mut self, _bus: &mut impl Bus) -> u8 { // 0x58, 1 byte, 2 cycles
+        self.clear_flag(FLAG_INTERRUPT);
+        2
+    }
+
+    fn clv_imp(&mut self, _bus: &mut impl Bus) -> u8 { // 0xB8, 1 byte, 2 cycles
+        self.clear_flag(FLAG_OVERFLOW);
+        2
+    }
+
+    fn cld_imp(&mut self, _bus: &mut impl Bus) -> u8 { // 0xD8, 1 byte, 2 cycles
+        self.clear_flag(FLAG_DECIMAL);
+        2
+    }
+
+    fn sei_imp(&mut self, _bus: &mut impl Bus) -> u8 { // 0x78, 1 byte, 2 cycles
+        self.set_flag(FLAG_INTERRUPT);
+        2
+    }
+
+    fn sed_imp(&mut self, _bus: &mut impl Bus) -> u8 { // 0xF8, 1 byte, 2 cycles
+        self.set_flag(FLAG_DECIMAL);
+        2
+    }
+
+    // all branching alternatives here all 1 bytes
+    fn bcs_rel(&mut self, bus: &mut impl Bus) -> u8 { self.branch(bus, self.flag(FLAG_CARRY)) } // 0xB0
+    fn bcc_rel(&mut self, bus: &mut impl Bus) -> u8 { self.branch(bus, !self.flag(FLAG_CARRY)) } // 0x90
     fn beq_rel(&mut self, bus: &mut impl Bus) -> u8 { self.branch(bus, self.flag(FLAG_ZERO)) } // 0xF0
     fn bne_rel(&mut self, bus: &mut impl Bus) -> u8 { self.branch(bus, !self.flag(FLAG_ZERO)) } // 0xD0
     fn bpl_rel(&mut self, bus: &mut impl Bus) -> u8 { self.branch(bus, !self.flag(FLAG_NEGATIVE)) } // 0x10
@@ -323,14 +359,20 @@ impl Cpu {
             0x00 => 1, // BRK imp
             0xEA => 1, // NOP
             0x38 => 1, // SEC imp 
-            0x90 => 2, // BCS rel
-            0xB0 => 2, // BCC rel
+            0x90 => 2, // BCC rel
+            0xB0 => 2, // BCS rel
             0xF0 => 2, // BEQ rel
             0xD0 => 2, // BNE rel
             0x10 => 2, // BPL rel
             0x30 => 2, // BMI rel
             0x50 => 2, // BVC rel
             0x70 => 2, // BVS rel
+            0x18 => 1, // CLC imp
+            0x58 => 1, // CLI imp
+            0xB8 => 1, // CLV imp
+            0xD8 => 1, // CLD imp
+            0x78 => 1, // SEI imp
+            0xF8 => 1, // SED imp
             _ => 1, // fallback, would show the invalid/unknown opcode only not its parameters
         }
     }