brokem implementation on main.rs - no regression

This commit is contained in:
2026-08-09 18:28:42 -05:00
parent d29dea2d25
commit 2964e6fad2
5 changed files with 181 additions and 18 deletions
+13 -7
View File
@@ -1,4 +1,4 @@
use crate::cartridge::Cartridge;
use crate::{cartridge::Cartridge, ppu::Ppu};
pub trait Bus {
fn read(&mut self, address: u16) -> u8;
@@ -8,32 +8,38 @@ pub trait Bus {
pub struct NesBus {
ram: [u8; 0x800], // 2KB fixed array, mirrors to fill $0000 to $1FFF
cart: Cartridge,
ppu: Ppu,
openbus: u8, // last byte on the CPU data bus
}
impl NesBus {
pub fn new(cart: Cartridge) -> Self {
Self { ram: [0; 0x800], cart }
Self { ram: [0; 0x800], cart, ppu: Ppu::new(), openbus: 0 }
}
}
impl Bus for NesBus {
fn read(&mut self, address: u16) -> u8 {
match address {
let result = match address {
0x0000..=0x1FFF => self.ram[(address & 0x07FF) as usize], // Zero-Page my beloved
0x2000..=0x3FFF => 0, //PPU registers stub, temporal
0x4000..=0x401F => 0, //APU controller stub, temporal
0x4020..=0x5FFF => 0, //Expansion ROM stub. temporal
0x2000..=0x3FFF => self.ppu.read(&mut self.cart, address, self.openbus),
0x4000..=0x401F => self.openbus, // APU regs: unmapped reads return bus contents
0x4020..=0x5FFF => self.openbus, // expansion: open bus
0x6000..=0x7FFF => self.cart.read_prg_ram(address), // SRAM reads from the cartridge
0x8000..=0xFFFF => self.cart.read_prg(address), // this is te space PRG Rom gets "loaded" to in real hardware
}
};
self.openbus = result;
result
}
fn write(&mut self, address: u16, value: u8) {
match address {
0x0000..=0x1FFF => self.ram[(address & 0x07FF) as usize] = value,
0x2000..=0x3FFF => self.ppu.write(&mut self.cart, address, value),
0x6000..=0x7FFF => self.cart.write_prg_ram(address, value),
0x8000..=0xFFFF => self.cart.write_prg(address, value),
_ => {} // Everything else dropped for now
}
self.openbus = value;
}
}