JakeBreath/rnes
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

implemented the INC and DEC family of instructions

Browse Source
This commit is contained in:
JakeBreath
2026-08-09 11:06:08 -05:00
parent ce5e94277e
commit 16b51620a6
3 changed files with 268 additions and 3 deletions
Download Patch File Download Diff File Expand all files Collapse all files
STATE.md
+4 -3
View File
@@ -24,7 +24,8 @@
- Batch 1 done (subroutines + stack): JSR, RTS, PHA, PLA, PHP, PLP, RTI, BRK, plus NOP and SEC as quick wins. Verified SP:FD->FB across JSR (push high-then-low works)
- Batch 2 done (branches): all 8 branches (BEQ/BNE/BCC/BCS/BPL/BMI/BVC/BVS) via one shared branch() routine with condition param. Taken = +3 cycles, page-cross = +1 more. Verified both taken and not-taken paths in the log
- Flag set/clear ops done (part of Batch 10): CLC, CLI, CLV, CLD, SEI, SED (SEC done in Batch 1). SEI/SED set, the rest clear. Fixed a real bug where SEI/SED were clearing instead of setting
- Trace now matches the nestest reference log through line 506 (CBB9 INY, CYC:1168), field-for-field (PC/A/X/Y/P/SP/CYC verified by label-comparison script). Next panic is on 0xC8 (INY) at line 506, top of Batch 8
- Trace now matches the nestest reference log through line 678 (CCBA TAY, CYC:1592), field-for-field (PC/A/X/Y/P/SP/CYC verified by label-comparison script). Next panic is on 0xA8 (TAY) at line 678, a Batch 10 transfer opcode
- Batch 8 done (inc/dec): INC (4 modes), DEC (4 modes), INX, INY, DEX, DEY. RMW cores (inc/dec) read-modify-write and correctly return base WITHOUT the page-cross extra (RMW cycles are fixed). Register ops are wrapping_add/sub with Z/N only. 124 of 151 official opcodes done. INY/INX carried the log from 506 to 678 lines
- Batch 3 done (loads): LDA (8 modes), LDX (5 modes), LDY (5 modes) via three shared cores (lda/ldx/ldy) + thin wrappers. Caught two real bugs in review: all 4 LDY wrappers called self.ldx (would write to X instead of Y), and 6 of 8 LDX/LDY wrappers had wrong base cycles (3 instead of 4). Both fixed
- Batch 4 done (stores): STA (7 modes), STX (3 modes), STY (3 modes) via three shared cores (sta/stx/sty) + thin wrappers. No flag changes. Refactored stx_zp to use the shared stx core for consistency. Fixed a comment typo (sta_abx was labeled 0x95 instead of 0x9D)
- Batch 5 done (compares): CMP (8 modes), CPX (3 modes), CPY (3 modes) via three shared cores (cmp/cpx/cpy) + wrappers + immediate variants. Sets C (reg >= mem), Z, N; no store. Uses wrapping_sub for the borrow math. 70 of 151 official opcodes done. No diff progress expected until the log reaches these opcodes
@@ -46,9 +47,9 @@ CPU implementation batches (by family, ordered by nestest log frequency):
- Batch 5 - DONE (compares, see Done section)
- Batch 6 - DONE (arithmetic, see Done section)
- Batch 7 - DONE (logic, see Done section)
- Batch 8 - Inc/Dec: INC/DEC 4 modes each (RMW), INX, INY, DEX, DEY. Next up
- Batch 8 - DONE (inc/dec, see Done section)
- Batch 9 - Shifts: ASL, LSR, ROL, ROR (accumulator + 4 memory modes each, RMW)
- Batch 10 - PARTIAL: flag ops done (CLC/CLI/CLV/CLD/SEI/SED, plus SEC/NOP). Remaining: JMP ind 6C, transfers TAX/TAY/TXA/TYA/TSX/TXS
- Batch 10 - PARTIAL: flag ops done (CLC/CLI/CLV/CLD/SEI/SED, plus SEC/NOP). Remaining: JMP ind 6C, transfers TAX/TAY/TXA/TYA/TSX/TXS. Next in log: TAY (0xA8) at line 678
Rules for each batch:
- Add the opcode's length to opcode_len in the same edit (never let them drift)